Add GPIOViewer partition info

This commit is contained in:
Theo Arends 2025-10-26 14:28:40 +01:00
parent b55f682c64
commit f19f206c0e
5 changed files with 84 additions and 87 deletions

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@ -113,7 +113,8 @@ const char WIFI_HOSTNAME[] = WIFI_DEFAULT_HOSTNAME; // Override by user_confi
#ifndef ARDUINO_ESP8266_RELEASE
#define ARDUINO_CORE_RELEASE "STAGE"
#else
#define ARDUINO_CORE_RELEASE ARDUINO_ESP8266_RELEASE
//#define ARDUINO_CORE_RELEASE ARDUINO_ESP8266_RELEASE // 2_7_8
#define ARDUINO_CORE_RELEASE "2.7.8"
#endif // ARDUINO_ESP8266_RELEASE
#ifndef USE_ADC_VCC
@ -194,7 +195,8 @@ const char WIFI_HOSTNAME[] = WIFI_DEFAULT_HOSTNAME; // Override by user_confi
#ifndef ARDUINO_ESP32_RELEASE
#define ARDUINO_CORE_RELEASE "STAGE"
#else
#define ARDUINO_CORE_RELEASE ARDUINO_ESP32_RELEASE
//#define ARDUINO_CORE_RELEASE ARDUINO_ESP32_RELEASE // 3_3_0
#define ARDUINO_CORE_RELEASE ESP_ARDUINO_VERSION_STR // 3.3.0
#endif // ARDUINO_ESP32_RELEASE
#ifdef USE_I2C_BUS2 // If defined for ESP8266 undefine first

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@ -1035,7 +1035,7 @@ void CmndStatus(void)
ESP_getFlashChipSize()/1024, ESP.getFlashChipRealSize()/1024
#endif // ESP8266
, ESP_getFlashChipId()
, ESP.getFlashChipSpeed()/1000000);
, ESP_getFlashChipSpeed()/1000000);
ResponseAppendFeatures();
XsnsDriverState();
ResponseAppend_P(PSTR(",\"Sensors\":"));

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@ -8,7 +8,7 @@
#ifdef ESP32
/*********************************************************************************************\
* ESP32, ESP32-S2, ESP32-S3, ESP32-C2, ESP32-C3, ESP32-C6 and ESP32-H2 Support
* ESP32, ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-H2, ESP32-P4, ESP32-S2 and ESP32-S3 Support
\*********************************************************************************************/
// 11b 11g 11n 11n 11ax
@ -16,54 +16,80 @@ const static char kWifiPhyMode[] PROGMEM = "low rate|11b|11g|HT20|HT40|HE20"; //
#include "soc/soc.h"
#include "soc/spi_reg.h"
// See libraries\ESP32\examples\ResetReason.ino
#include "esp_chip_info.h"
#include <nvs.h>
#include "Esp.h"
#include "spi_flash_mmap.h"
#include <memory>
#include <soc/soc.h>
#include <soc/efuse_reg.h>
#include <esp_partition.h>
extern "C" {
#include "esp_ota_ops.h"
#include "esp_image_format.h"
}
#include "esp_system.h"
#include "esp_flash.h"
#include "bootloader_common.h"
// ESP32_ARCH contains the name of the architecture (used by autoconf)
#if CONFIG_IDF_TARGET_ESP32
// Flash memory mapping - See Esp.cpp
#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
#ifdef CORE32SOLO1
#define ESP32_ARCH "esp32solo1"
#else
#define ESP32_ARCH "esp32"
#endif
#include "esp32/rom/rtc.h"
#include "esp32/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x1000 // Flash offset containing magic flash size and spi mode
#elif CONFIG_IDF_TARGET_ESP32S2
#define ESP32_ARCH "esp32s2"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x1000 // Flash offset containing magic flash size and spi mode
#elif CONFIG_IDF_TARGET_ESP32S3
#define ESP32_ARCH "esp32s3"
#include "esp32s3/rom/rtc.h"
#include "esp32s3/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32s3 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32C2
#define ESP32_ARCH "esp32c2"
#include "esp32c2/rom/rtc.h"
#include "esp32c2/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c2 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32C3
#define ESP32_ARCH "esp32c3"
#include "esp32c3/rom/rtc.h"
#include "esp32c3/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c3 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32C5
#define ESP32_ARCH "esp32c5"
#include "esp32c5/rom/rtc.h"
#include "esp32c5/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32c5 is located at 0x2000
#elif CONFIG_IDF_TARGET_ESP32C6
#define ESP32_ARCH "esp32c6"
#include "esp32c6/rom/rtc.h"
#include "esp32c6/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c6 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32H2
#define ESP32_ARCH "esp32h2"
#include "esp32h2/rom/rtc.h"
#include "esp32h2/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32h2 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32P4
#define ESP32_ARCH "esp32p4"
#include <esp_phy_init.h>
#include "esp32p4/rom/rtc.h"
#include "esp32p4/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32p4 is located at 0x2000
#else
#define ESP32_ARCH ""
#endif
// See libraries\ESP32\examples\ResetReason.ino
#include "esp_chip_info.h"
#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2 // ESP32-S2
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S3 // ESP32-S3
#include "esp32s3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C2 // ESP32-C2
#include "esp32c2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3 // ESP32-C3
#include "esp32c3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C5 // ESP32-C5
#include "esp32c5/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C6 // ESP32-C6
#include "esp32c6/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32H2 // ESP32-H2
#include "esp32h2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4
#include "esp32p4/rom/rtc.h"
#else
#error Target CONFIG_IDF_TARGET is not supported
#endif
@ -72,14 +98,8 @@ size_t getArduinoLoopTaskStackSize(void) {
return SET_ESP32_STACK_SIZE;
}
#ifndef CONFIG_IDF_TARGET_ESP32P4
#include <esp_phy_init.h>
#endif
// Handle 20k of NVM
#include <nvs.h>
bool NvmExists(const char *sNvsName) {
nvs_handle_t handle;
if (nvs_open(sNvsName, NVS_READONLY, &handle) != ESP_OK) {
@ -219,57 +239,6 @@ void NvsInfo(void) {
nvs_stats.used_entries, nvs_stats.total_entries, nvs_stats.namespace_count);
}
//
// Flash memory mapping
//
// See Esp.cpp
#include "Esp.h"
#include "spi_flash_mmap.h"
#include <memory>
#include <soc/soc.h>
#include <soc/efuse_reg.h>
#include <esp_partition.h>
extern "C" {
#include "esp_ota_ops.h"
#include "esp_image_format.h"
}
#include "esp_system.h"
#include "esp_flash.h"
#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
#include "esp32/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x1000 // Flash offset containing magic flash size and spi mode
#elif CONFIG_IDF_TARGET_ESP32S2 // ESP32-S2
#include "esp32s2/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x1000 // Flash offset containing magic flash size and spi mode
#elif CONFIG_IDF_TARGET_ESP32S3 // ESP32-S3
#include "esp32s3/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32s3 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32C2 // ESP32-C2
#include "esp32c2/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c2 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32C3 // ESP32-C3
#include "esp32c3/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c3 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32C5 // ESP32-C5
#include "esp32c5/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32c5 is located at 0x2000
#elif CONFIG_IDF_TARGET_ESP32C6 // ESP32-C6
#include "esp32c6/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c6 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32H2 // ESP32-H2
#include "esp32h2/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32h2 is located at 0x0000
#elif CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4
#include "esp32p4/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32p4 is located at 0x2000
#else
#error Target CONFIG_IDF_TARGET is not supported
#endif
#include "bootloader_common.h"
uint32_t EspProgramSize(const char *label) {
const esp_partition_t *part = esp_partition_find_first(ESP_PARTITION_TYPE_APP, ESP_PARTITION_SUBTYPE_ANY, label);
if (!part) {
@ -582,6 +551,14 @@ uint8_t* FlashDirectAccess(void) {
return data;
}
uint32_t ESP_getFlashChipSpeed(void) {
#if ESP_ARDUINO_VERSION >= ESP_ARDUINO_VERSION_VAL(3, 3, 2)
return ESP.getFlashFrequencyMHz() * 1000000;
#else
return ESP.getFlashChipSpeed(); // In Hz
#endif
}
uint32_t ESP_getPsramSize(void) {
return ESP.getPsramSize();
}

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@ -120,6 +120,10 @@ uint32_t ESP_getFlashChipSize(void) {
return ESP.getFlashChipSize();
}
uint32_t ESP_getFlashChipSpeed(void) {
return ESP.getFlashChipSpeed();
}
uint32_t ESP_getPsramSize(void) {
return 0;
}

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@ -374,7 +374,7 @@ void GVHandleEspInfo(void) {
appendField("flash_chip_size", String(ESP.getFlashChipRealSize()), false);
#endif
appendField("flash_chip_speed", String(ESP.getFlashChipSpeed()), false);
appendField("flash_chip_speed", String(ESP_getFlashChipSpeed()), false);
appendField("heap_size", String(ESP_getHeapSize()), false);
appendField("heap_max_alloc", String(ESP_getMaxAllocHeap()), false);
appendField("psram_size", String(ESP_getPsramSize()), false);
@ -441,6 +441,7 @@ void GVHandlePartition(void) {
String jsonResponse = "["; // Start of JSON array
#ifdef ESP32
bool firstEntry = true; // Used to format the JSON array correctly
const esp_partition_t *cur_part = esp_ota_get_running_partition();
auto appendPartitions = [&](esp_partition_type_t type) {
esp_partition_iterator_t iter = esp_partition_find(type, ESP_PARTITION_SUBTYPE_ANY, NULL);
@ -455,7 +456,20 @@ void GVHandlePartition(void) {
// Append partition information in JSON format
jsonResponse += "{";
jsonResponse += "\"label\":\"" + String(partition->label) + "\",";
// jsonResponse += "\"label\":\"" + String(partition->label) + "\",";
String label = partition->label;
if (label == "spiffs") {
label = "littlefs";
}
else if ((label == "app0") || (label == "app1")) {
if (label = String(cur_part->label)) {
label = "tasmota-" + String(CODE_IMAGE_STR);
label.toLowerCase();
}
}
jsonResponse += "\"label\":\"" + label + "\",";
jsonResponse += "\"type\":" + String(partition->type) + ",";
jsonResponse += "\"subtype\":" + String(partition->subtype) + ",";
jsonResponse += "\"address\":\"0x" + String(partition->address, HEX) + "\",";