58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
//
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// Adds Cortex-M4/M7 SIMD instruction intrinsics for M4/M7 targets missing
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// this support in their board support packages (e.g. Teensyduino)
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//
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#ifndef __CM4_SIMD__
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#define __CM4_SIMD__
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#define __SSAT16(ARG1, ARG2) \
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__extension__ \
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({ \
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int32_t __RES, __ARG1 = (ARG1); \
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__asm volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
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__RES; \
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})
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#define __USAT16(ARG1, ARG2) \
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__extension__ \
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({ \
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uint32_t __RES, __ARG1 = (ARG1); \
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__asm volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
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__RES; \
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})
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__attribute__((always_inline)) static inline uint32_t __SADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__asm volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__((always_inline)) static inline uint32_t __SSUB16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__asm volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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__attribute__((always_inline)) static inline uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
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{
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uint32_t result;
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__asm volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
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return(result);
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}
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__attribute__((always_inline)) static inline uint32_t __QADD16(uint32_t op1, uint32_t op2)
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{
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uint32_t result;
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__asm ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
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return(result);
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}
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#endif
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